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infineon technologies 12.99 3.3v 16m x 64/72-bit 1 bank sdram module 3.3v 32m x 64/72-bit 2 bank sdram module 168 pin unbuffered dimm modules hys64/72v16300gu hys64/72v32220gu ? 168 pin unbuffered 8 byte dual-in-line sdram modules for pc main memory applications ? pc100 & pc133 versions ? 1 bank 16m x 64, 16m x 72 and 2 bank 132m x 64, 32m x 72 organisation ? optimized for byte-write non-parity (x64) or ecc (x72) applications ? jedec standard synchronous drams (sdram) ? fully pc board layout compatible to intels rev. 1.0 module specification ? sdram performance: ? programmed latencies : ? single +3.3v( 0.3v ) power supply ? programmable cas latency, burst length and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? decoupling capacitors mounted on substrate ? all inputs, outputs are lvttl compatible ? serial presence detect with e 2 prom ? utilizes 16m x 8 sdrams in tsopii-54 packages with 4096 refresh cycles every 64 ms ? 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads -7.5 -8 units pc133 pc100 f ck clock frequency (max.) 133 100 mhz t ac clock access time 5.4 6 ns product speed cl trcd trp -7.5 pc133 3 3 3 -8 pc100 2 2 2 18.99
hys64(72)v16300/32220gu sdram-modules infineon technologies 2 12.99 the hys64(72)16300gu and hys64(72)32220 are industry standard 168-pin 8-byte dual in-line memory modules (dimms) which are organised as 16m x 64, 16m x 72 in one bank and 32m x 64 and 32m x 72 in two banks high speed memory arrays designed with 128m synchronous drams (sdrams) for non-parity and ecc applications. the dimms use -7.5 speed sorted 16m x 8 sdram devices in tsop54 packages to meet the pc133-333 requirements and -8 & -8a components for the standard pc100 applications. decoupling capacitors are mounted on the pc board. the pc board design is according to intels pc sdram rev. 1.0 module specification.the dimms have a serial presence detect, implemented with a serial e 2 prom using the two pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168-pin dimms provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with 1,25 ( 31,75 mm) height. ordering information note: all partnumbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: hys64v16300gu-8-c, indicating rev.c dies are used for sdram components. pin names address format: type code package descriptions module height 64mbyte dimms: hys 64v16300gu-7.5-... pc133-333-520 l-dim-168-33 133 mhz 16m x 64 1 bank sdram module 1,25 hys 72v16300gu-7.5-... pc133-333-520 l-dim-168-33 133 mhz 16m x 72 1 bank sdram module 1,25 hys 64v16300gu-8-... pc100-222-620 l-dim-168-33 100 mhz 16m x 64 1 bank sdram module 1,25 hys 72v16300gu-8-... pc100-222-620 l-dim-168-33 100 mhz 16m x 72 1 bank sdram module 1,25 128 mbyte dimms: hys 64v32220gu-7.5-... pc133-333-520 l-dim-168-30 133 mhz 32m x 64 2 bank sdram module 1,25 hys 64v32220gu-7.5-... pc133-333-520 l-dim-168-30 133 mhz 32m x 72 2 bank sdram module 1,25 hys 64v32220gu-8-... pc100-222-620 l-dim-168-30 100 mhz 32m x 64 2 bank sdram module 1,25 hys 72v32220gu-8-... pc100-222-620 l-dim-168-30 100 mhz 32m x 72 2 bank sdram module 1,25 a0-a11 address inputs we read / write input vss ground ba0, ba1 bank selects cke0 , cke1 clock enable scl clock for spd dq0 - dq63 data input/output clk0 - clk3 clock input sda serial data out cb0-cb7 check bits (x72 only) dqmb0 - dqmb7 data mask n.c. no connection ras row address strobe cs0 - cs3 chip select cas column address strobe vcc power (+3.3 volt) part number rows columns bank select refresh period interval 16m x 64 hys 64v16300gu 12 10 2 4k 64 ms 15,6 m s 16m x 72 hys 72v16300gu 12 10 2 4k 64 ms 15,6 m s 32m x 64 hys 64v32220gu 12 10 2 4k 64 ms 15,6 m s 32m x 72 hys 72v32220gu 12 10 2 4k 64 ms 15,6 m s
hys64(72)v16300/32220gu sdram-modules infineon technologies 3 12.99 pin configuration note : pinnames in brackets are for the x72 ecc versions pin # symbol pin # symbol pin # symbol pin # symbol 1 vss 43 vss 85 vss 127 vss 2 dq0 44 du 86 dq32 128 cke0 3 dq1 45 cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 vcc 48 du 90 vcc 132 nc 7 dq4 49 vcc 91 dq36 133 vcc 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 nc (cb2) 94 dq39 136 cb6 11 dq8 53 nc (cb3) 95 dq40 137 cb7 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vcc 101 dq45 143 vcc 18 vcc 60 dq20 102 vcc 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 du 104 dq47 146 du 21 nc (cb0) 63 cke1 105 nc (cb4) 147 nc 22 nc (cb1) 64 vss 106 nc (cb5) 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vcc 68 vss 110 vcc 152 vss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 vcc 115 ras 157 vcc 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 clk2 121 a9 163 clk3 38 a10 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 vcc 82 sda 124 vcc 166 sa1 41 vcc 83 scl 125 clk1 167 sa2 42 clk0 84 vcc 126 nc 168 vcc
hys64(72)v16300/32220gu sdram-modules infineon technologies 4 12.99 block diagram for 8m x 64/72 sdram dimm modules (hys64/72v82(3)00gu) spb03958 dq0-dq7 dqm we d0 cs0 we dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm d4 dq0-dq7 dq(15:8) dqmb1 dqm d1 cs dq0-dq7 dq(47:40) dqmb5 dqm d5 dq0-dq7 cb(7:0) dqm cs d8 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs2 cs cs cs d3 d2 dqmb7 dq(63:56) dqmb6 dq(55:48) cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm a0-a11, ba0, ba1 d0-d7, (d8) cc v ss v c0-c15, (c16, c17) d0-d7, (d8) ras d0-d7, (d8) d0-d7, (d8) cas clock wiring 8 m x 64 8 m x 72 clk0 4 sdram + 3.3 pf 5 sdram termination termination clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 clk3 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp w cs cs we we we we cs we we we we d0-d7, (d8) cke0 d0-d7, (d8) termination termination note: d8 is only used in the x72 ecc version.
hys64(72)v16300/32220gu sdram-modules infineon technologies 5 12.99 block diagram for 16m x 64/72 sdram dimm modules (hys64/72v1620gu) spb03769 dq0-dq7 dqm cs d0 dq0-dq7 dqm d8 cs cs0 cs1 dq(7:0) dqmb0 dq0-dq7 dq(39:32) dqmb4 dqm cs d4 cs dq0-dq7 dqm d12 dq0-dq7 dq(15:8) dqmb1 dqm cs d1 cs dq0-dq7 dqm d9 dq0-dq7 dq(47:40) dqmb5 dqm cs cs d5 dqm dq0-dq7 d13 dq0-dq7 cb(7:0) dqm cs cs d16 dqm dq0-dq7 d17 dq0-dq7 dq0-dq7 dq(31:24) dqmb3 dq(23:16) dqmb2 dqm dqm cs3 cs2 cs cs cs cs cs cs d3 dq0-dq7 dqm d2 dqm dq0-dq7 dqmb7 dq(63:56) d11 dqmb6 dq(55:48) d10 cs d7 d6 dq0-dq7 dqm dq0-dq7 dqm cs dq0-dq7 dqm d15 dqm dq0-dq7 d14 a0-a11, ba0, ba1 d0-d15, (d16, d17) dd v ss v c0-c31, (c32...c35) d0-d15, (d16, d17) d0-d7, (d8) ras, cas, we d0-d15, (d16, d17) d0-d7, (d16) cke0 d9-d15, (d17) cke1 dd v 10 k w clock wiring 16 m x 64 16 m x 72 clk0 4 sdram + 3.3 pf 5 sdram 5 sdram 4 sdram + 3.3 pf clk1 4 sdram + 3.3 pf 4 sdram + 3.3 pf clk2 4 sdram + 3.3 pf clk3 4 sdram + 3.3 pf 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp w note: d16 & d17 is only used in the x72 ecc version and all resistor values are 10 except otherwise noted. w
hys64(72)v16300/32220gu sdram-modules infineon technologies 6 12.99 dc characteristics t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input high voltage v i h 2.0 vcc+0.3 v input low voltage v i l C 0.5 0.8 v output high voltage ( i out = C 4.0 ma) v oh 2.4 C v output low voltage ( i out = 4.0 ma) v ol C0.4v input leakage current, any input (0 v < v i n < 3.6 v, all other inputs = 0 v) i i (l) C 40 40 m a output leakage current (dq is disabled, 0 v < v out < v cc ) i o(l) C 40 40 m a parameter symbol limit values unit max. 16mx64 max. 16mx72 max. 32mx64 max. 32mx72 input capacitance (a0 to a11, ba0, ba1, ras , cas , we ) c i 1 65 72 105 144 pf input capacitance (cs0 -cs3, ) c i 2 32 40 32 40 pf input capacitance ( clk0 - clk3 ) c i cl 35 38 35 38 pf input capacitance (cke0, cke1) c i 3 65 72 65 72 pf input capacitance (dqmb0 - dqmb7) c i 4 13 13 20 20 pf input / output capacitance (dq0-dq63, cb0-cb7) c i o 10 10 15 15 pf input capacitance (scl,sa0-2) c sc 8888pf input/output capacitance c sd 10 10 10 10 pf
hys64(72)v16300/32220gu sdram-modules infineon technologies 7 12.99 operating currents per sdram component (t a = 0 to 70 o c, vdd = 3.3v 0.3v 1) (recommended operating conditions unless otherwise noted)) parameter & test condition symb. -7.5 -8 note max. operating current trc=trcmin., tck=tckmin. ouputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access icc1 130 120 ma 1 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 1.5 ma 1 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 40 35 ma 1 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 50 45 ma 1 cke<=vil(max.) icc3p 10 ma 1 burst operating current tck = min., read command cycling icc4 130 120 ma 1,2 auto refresh current tck = min., auto refresh command cycling icc5 180 170 ma 1 self refresh current self refresh mode, cke=0.2v standard version icc6 1.5 ma 1
hys64(72)v16300/32220gu sdram-modules infineon technologies 8 12.99 ac characteristics 3)4) t a = 0 to 70 c; v ss = 0 v; v cc = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 10 C C 10 10 C C ns ns system frequency cas latency = 3 cas latency = 2 f ck C C 133 100 C C 100 100 mhz mhz clock access time cas latency = 3 cas latency = 2 t ac C C 5.4 6 C C 6 6 ns ns 4,5) clock high pulse width t ch 2.5 C 3 C ns 6) clock low pulse width t cl 2.5 C 3 C ns 6) set and hold parameters input setup time t is 1.5 C 2 C ns 7) input hold time t ih 0.8 C 1 C ns 7) power down mode entry time t sb C1C1clk 8) power down mode exit setup time t pde 1C1Cclk 9) mode register setup time t rcs 2C2Cclk transition time (rise and fall) t t 1C1Cns common parameters ras to cas delay t rcd 20C20Cns precharge time t rp 20C20Cns active command period t ras 45 100k 50 100k ns cycle time t rc 67.5 C 70 C ns bank to bank delay time t rrd 15C16Cns cas to cas delay time (same bank) t ccd 1C1Cclk
hys64(72)v16300/32220gu sdram-modules infineon technologies 9 12.99 refresh cycle refresh period (4096 cycles) t ref C64C64ms self refresh exit time t srex 1C1Cclk 10) read cycle data out hold time t oh 3C3Cns 4) data out to low impedance t lz 0C0Cns data out to high impedance t hz 3738ns 11) dqm data out disable latency t dqz C2C2clk write cycle data input to precharge (write recovery) t wr 2C2 C clk dqm write mask latency t dqw 0C0Cclk parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max.
hys64(72)v16300/32220gu sdram-modules infineon technologies 10 12.99 notes: 1. these parameters depend on the cycle rate. these values are measured at 133 mhz for -7.5 and at 100 mhz for -8 modules. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. all values are shown per memory component. 2. these parameters are measured with continous data stream during read access and all dq toggling. cl=3 and bl=4 assumed and the vddq current is excluded. 3. all ac characteristics are shown on sdram component level. an initial pause of 100 m s is required after power-up, then a precharge all banks command must be given followed by 8 auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit show. specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v. 5. if clock rising time is longer than 1ns, a time (t t /2 -0.5) ns has to be added to this parameter. 6. rated at 1.5 v 7. if t t is longen than 1 ns, a time (t t -1) ns has to be added to this parameter. 8. anytime the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 9. timing is asynchronous. if setup time is not met by rising edge of the clock then the cke signal is assumed latched on the next cycle. 10.self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 11.referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 50 pf i/o measurement conditions for tac and toh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hys64(72)v16300/32220gu sdram-modules infineon technologies 11 12.99 spd-table for pc133 modules: byte# description spd entry value hex 16mx64 -7.5 16mx72 -7.5 32mx64 -7.5 32mx72 -7.5 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addres- ses(for 8mx8 sdrams) 10 0a 5 number of dimm banks 1 / 2 01 02 6 module data width 64 / 72 40 48 40 48 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 7.5 ns 75 10 sdram access time from clock at cl=3 5.4 ns 54 11 dimm config none / ecc 00 02 00 02 12 refresh rate/type self-refresh, 15.6 m s 80 1 3 s d r a m w i d t h , p r i m a r y x 8 0 8 14 error checking sdram data width n/a / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 min. clock cycle time at cas latency = 2 10.0 ns a0 24 max. data access time from clock for cl=2 6.0 ns 60 25 minimum clock cycle time at cl = 1 not supported ff 26 maximum data access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay trrd 15 ns 0f
hys64(72)v16300/32220gu sdram-modules infineon technologies 12 12.99 byte# description spd entry value hex 16mx64 -7.5 16mx72 -7.5 32mx64 -7.5 32mx72 -7.5 29 minimum ras to cas delay trcd 20 ns 14 30 minimum ras pulse width tras 45 ns 2d 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 1.5 ns 15 33 sdram input hold time 0.8 ns 08 34 sdram data input hold time 1.5 ns 15 35 sdram data input setup time 0.8 ns 08 62-61 superset information (may be used in future) ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 13 25 14 26 64- 125 manufacturers information (optional) (ffh if not used) xx xx xx xx 126 frequency specification 64 127 133 mhz support details af ff 128+ unused storage locations ff
hys64(72)v16300/32220gu sdram-modules infineon technologies 13 12.99 spd-table for pc100 modules: byte# description spd entry value hex 16mx64 -8 16mx72 -8 32mx64 -8 32mx72 -8 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12 0c 4 number of column addres- ses(for 8mx8 sdrams) 10 0a 5 number of dimm banks 1 / 2 01 02 6 module data width 64 / 72 40 48 40 48 7 module data width (contd) 0 00 8 module interface levels lvttl 01 9 sdram cycle time at cl=3 10.0 ns a0 10 sdram access time from clock at cl=3 6.0 ns 60 11 dimm config none / ecc 00 02 00 02 12 refresh rate/type self-refresh, 15.6 m s 80 1 3 s d r a m w i d t h , p r i m a r y x 8 0 8 14 error checking sdram data width n/a / x8 00 08 00 08 15 minimum clock delay for back-to-back random column address t ccd = 1 clk 01 16 burst length supported 1, 2, 4 & 8 0f 17 number of sdram banks 4 04 18 supported cas latencies cas latency = 2 & 3 06 19 cs latencies cs latency = 0 01 20 we latencies write latency = 0 01 21 sdram dimm module attributes non buffered/non reg. 00 22 sdram device attributes :general vcc tol +/- 10% 0e 23 min. clock cycle time at cas latency = 2 10.0 ns a0 24 max. data access time from clock for cl=2 6.0 ns 60 25 minimum clock cycle time at cl = 1 not supported ff 26 maximum data access time from clock at cl=1 not supported ff 27 minimum row precharge time 20 ns 14 28 minimum row active to row active delay trrd 16 ns 10
hys64(72)v16300/32220gu sdram-modules infineon technologies 14 12.99 byte# description spd entry value hex 16mx64 -8 16mx72 -8 32mx64 -8 32mx72 -8 29 minimum ras to cas delay trcd 20 ns 14 30 minimum ras pulse width tras 45 ns 2d 31 module bank density (per bank) 128 mbyte 20 32 sdram input setup time 2 ns 20 33 sdram input hold time 1 ns 10 34 sdram data input hold time 2 ns 20 35 sdram data input setup time 1 ns 10 62-61 superset information (may be used in future) ff 62 spd revision revision 1.2 12 63 checksum for bytes 0 - 62 71 83 72 84 64- 125 manufacturers information (optional) (ffh if not used) xx xx xx xx 126 frequency specification 100 mhz 64 127 100 mhz support details af ff 128+ unused storage locations ff
hys64(72)v16300/32220gu sdram-modules infineon technologies 15 12.99 l-dim-168-30 sdram dimm module package hys64/72v32220gu gld09159 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 0.1 85 94 95 124 125 168 2 17.78 0.1 4 3 min. 4 31.75 detail of contacts min. 2.54 1 0.05 1.27 1 1.27 91 x 1.27 = 115.57 3.125 0.2 0.15 4.45 2.26 8.25 +0.1 r1.27 *) on ecc modules only *) *)
hys64(72)v16300/32220gu sdram-modules infineon technologies 16 12.99 l-dim-168-33 sdram dimm module package hys64/72v16300gu 133,35 1 84 17,78 10 11 40 41 85 3,0 127,35 168 124 125 66,68 42,18 6,35 2,0 3,125 detail b 6,35 2,0 3,125 detail a detail c 2,54 min. 1,27 1,0 + 0.5 - a b c x) x ) on ecc modules onl y + - 0,2 0,15 31.75 94 95 1,27 + 0.1 - dm168-33.wm f 4,0 max.
hys64(72)v16300/32220gu sdram-modules infineon technologies 17 12.99 update releases: june 1, 1999 explanation for factory specific code in part numbers added june 17, 1999 byte 22 for pc100 modules changed from 06 to 0e august 3, 1999 pc133 spec incorpoated august 5, 1999 spd tables added august 23, 1999 byte 126 changed to 64h for pc133 modules sept.30, 1999 some errors corrected, checksums added dec. 2, 1999 some timing parameters adjusted according to intels pc133 specification -8a speedsort removed
hys64(72)v16300/32220gu sdram-modules infineon technologies 18 12.99

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